The present disclosure relates generally to junction field effect transistors (JFETs), and more particularly to gate region structures for JFETs.
A JFET is a field effect transistor device that provides the capability of modulating current through a channel region between the drain and the source of the JFET. The current through the channel region is controlled by adjusting the voltage applied to a p-n junction proximate the gate of the JFET. In normally off JFETs, or enhancement mode JFETs, the depletion width of the p-n junction typically extends all the way across the channel region of the JFET when about 0V is applied to the gate. Application of a positive voltage to the gate forward biases the p-n junction and reduces the width of the depletion region in the channel region. This creates a conduction path for current in the channel region between the source and drain of the JFET. In this regard, a normally off JFET can be used as a controllable switch for power electronics applications.
FIG. 1 depicts a conventional normally off JFET device 100. As illustrated, JFET device 100 includes a source terminal 110, a drain terminal 120, and a gate terminal 130. Source terminal 110 is coupled to source contacts 112. Drain terminal 120 is coupled to drain contact 122. Gate terminal 130 is coupled to gate contacts 132. A gate region 140 of semiconductor material is adjacent each gate contact 132. A channel region 150 of semiconductor material is disposed between adjacent gate regions 140 and under source contact 112. A drift region 160 of semiconductor material is disposed between, on one side, gate regions 140 and channel regions 150, and, on the other side, drain contact 122.
JFET device 100 illustrated in FIG. 1 is an n-channel normally off JFET such that channel region 150 and drift region 160 are n-type semiconductor materials. Gate region 140 is of a p-type semiconductor material to form a p-n junction 145 between gate region 140 and channel region 150. Another p-n junction 146 is formed between gate region 140 and drift region 160. P-n junction 145 has a depletion region 155 with a depletion width that extends across channel region 150 when a 0V is applied to gate contact 132. When the voltage applied to gate contact 132 reaches a threshold voltage, p-n junction 145 becomes forward-biased and the width of depletion region 155 is reduced. This creates a channel in channel region 150 for conduction of current between drain contact 122 and source contact 112.
Conventional normally off JFETs, such as silicon carbide (SiC) JFETs, turn on at low threshold gate voltages, such as at about 1V, and are fully on at low gate voltages, such as at about 3V. These voltage levels are not compatible with conventional MOSFET gate drivers, which operate between about 0V (off-state) and about 15V (on-state). The threshold voltage of a conventional normally off SiC JFET of about 1V is so low that it is not safe to use a normally off SiC JFET with a MOSFET gate driver in power electronics applications, where noise could be higher than about 1V. Additionally, a 15V gate voltage would cause the p-n junction between gate and source to conduct a very large current, which can cause significant losses and defect propagation and subsequent device failure in the SiC material. In this regard, a specially designed gate driver is typically required for operation of SiC JFETs, which limits the application of JFETs in power electronics.
In a conventional normally off JFET, the gate source region forms a p-n junction which conducts a gate source current when the p-n junction is forward biased. The gate source current can be about 50 mA or even higher, which causes power losses in WET driver circuits. Moreover, the p-n junction in a conventional normally off JFET is almost fully forward biased when the JFET is turned on and the width of the depletion region of the p-n junction is very thin. The thin depletion region between the gate and channel can introduce a high gate source capacitance, which can limit dynamic performance of the JFET significantly.
Thus, there is a need for a normally off SiC JFET structure that is compatible with MOSFET drivers that overcomes the above-mentioned disadvantages.